Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

Subscribe to email list

Please select the email list(s) to which you wish to subscribe.

You are here

Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

TitleParametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models
Publication TypeJournal Article
Year of Publication1991
AuthorsYu, TK, Kang, SM, Sacks, J, Welch, WJ
JournalInternational journal of circuit theory and applications
Volume19
Pagination579–592
URLhttp://onlinelibrary.wiley.com/doi/10.1002/cta.4490190606/abstract